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Material Selection for Minimizing Direct Tunneling in Nanowire Transistors

Identifieur interne : 001866 ( Main/Repository ); précédent : 001865; suivant : 001867

Material Selection for Minimizing Direct Tunneling in Nanowire Transistors

Auteurs : RBID : Pascal:12-0318010

Descripteurs français

English descriptors

Abstract

When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field-effect transistors (FETs) and tunnel FETs. Therefore, a survey of materials in a nanowire geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge, and carbon nanotubes. The tunneling effective mass gives the best indication of the relative size of the tunnel currents when comparing two different materials of any type. The indirect-gap materials, Si and Ge, give the largest tunneling masses in the conduction band, and they give the smallest conduction band tunnel currents within the range of diameters considered. Si gives the lowest overall tunnel current for both the conduction and valence bands, and therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. A semianalytic approach to calculating tunnel current is demonstrated, which requires considerably less computation than a full-band numerical calculation.

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Pascal:12-0318010

Le document en format XML

<record>
<TEI>
<teiHeader>
<fileDesc>
<titleStmt>
<title xml:lang="en" level="a">Material Selection for Minimizing Direct Tunneling in Nanowire Transistors</title>
<author>
<name sortKey="Sarwat Sylvia, Somaia" uniqKey="Sarwat Sylvia S">Somaia Sarwat Sylvia</name>
<affiliation wicri:level="1">
<inist:fA14 i1="01">
<s1>Department of Electrical Engineering, University of California</s1>
<s2>Riverside, CA 92521-0204</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>Riverside, CA 92521-0204</wicri:noRegion>
</affiliation>
<affiliation wicri:level="1">
<inist:fA14 i1="02">
<s1>Intel Corporation</s1>
<s2>Hillsboro, OR 97124-5961</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>Intel Corporation</wicri:noRegion>
</affiliation>
</author>
<author>
<name sortKey="Park, Hong Hyun" uniqKey="Park H">Hong-Hyun Park</name>
<affiliation wicri:level="1">
<inist:fA14 i1="01">
<s1>Department of Electrical Engineering, University of California</s1>
<s2>Riverside, CA 92521-0204</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>Riverside, CA 92521-0204</wicri:noRegion>
</affiliation>
<affiliation wicri:level="1">
<inist:fA14 i1="02">
<s1>Intel Corporation</s1>
<s2>Hillsboro, OR 97124-5961</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>Intel Corporation</wicri:noRegion>
</affiliation>
</author>
<author>
<name sortKey="Abul Khayer, M" uniqKey="Abul Khayer M">M. Abul Khayer</name>
<affiliation wicri:level="1">
<inist:fA14 i1="01">
<s1>Department of Electrical Engineering, University of California</s1>
<s2>Riverside, CA 92521-0204</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>Riverside, CA 92521-0204</wicri:noRegion>
</affiliation>
<affiliation wicri:level="1">
<inist:fA14 i1="02">
<s1>Intel Corporation</s1>
<s2>Hillsboro, OR 97124-5961</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>Intel Corporation</wicri:noRegion>
</affiliation>
</author>
<author>
<name sortKey="Alam, Khairul" uniqKey="Alam K">Khairul Alam</name>
<affiliation wicri:level="1">
<inist:fA14 i1="03">
<s1>Department of Electrical and Electronic Engineering, East West University</s1>
<s2>Dhaka 1212</s2>
<s3>BGD</s3>
<sZ>4 aut.</sZ>
</inist:fA14>
<country>Bangladesh</country>
<wicri:noRegion>Dhaka 1212</wicri:noRegion>
</affiliation>
</author>
<author>
<name sortKey="Klimeck, Gerhard" uniqKey="Klimeck G">Gerhard Klimeck</name>
<affiliation wicri:level="1">
<inist:fA14 i1="01">
<s1>Department of Electrical Engineering, University of California</s1>
<s2>Riverside, CA 92521-0204</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>Riverside, CA 92521-0204</wicri:noRegion>
</affiliation>
<affiliation wicri:level="1">
<inist:fA14 i1="02">
<s1>Intel Corporation</s1>
<s2>Hillsboro, OR 97124-5961</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>Intel Corporation</wicri:noRegion>
</affiliation>
</author>
<author>
<name sortKey="Lake, Roger K" uniqKey="Lake R">Roger K. Lake</name>
<affiliation wicri:level="1">
<inist:fA14 i1="04">
<s1>Network for Computational Nanotechnology, Purdue University</s1>
<s2>West Lafayette IN 47907</s2>
<s3>USA</s3>
<sZ>6 aut.</sZ>
</inist:fA14>
<country>États-Unis</country>
<wicri:noRegion>West Lafayette IN 47907</wicri:noRegion>
</affiliation>
</author>
</titleStmt>
<publicationStmt>
<idno type="inist">12-0318010</idno>
<date when="2012">2012</date>
<idno type="stanalyst">PASCAL 12-0318010 INIST</idno>
<idno type="RBID">Pascal:12-0318010</idno>
<idno type="wicri:Area/Main/Corpus">001A13</idno>
<idno type="wicri:Area/Main/Repository">001866</idno>
</publicationStmt>
<seriesStmt>
<idno type="ISSN">0018-9383</idno>
<title level="j" type="abbreviated">IEEE trans. electron devices</title>
<title level="j" type="main">I.E.E.E. transactions on electron devices</title>
</seriesStmt>
</fileDesc>
<profileDesc>
<textClass>
<keywords scheme="KwdEn" xml:lang="en">
<term>Binary compound</term>
<term>Carbon nanotubes</term>
<term>Conduction band</term>
<term>Direct current</term>
<term>Effective mass</term>
<term>Field effect transistor</term>
<term>Gallium nitride</term>
<term>Ge-Si alloys</term>
<term>Germanium</term>
<term>Indium antimonides</term>
<term>Indium phosphide</term>
<term>Leakage current</term>
<term>Material selection</term>
<term>Nanoelectronics</term>
<term>Nanowires</term>
<term>Tunnel effect</term>
<term>Tunnel transistors</term>
<term>Valence band</term>
</keywords>
<keywords scheme="Pascal" xml:lang="fr">
<term>Choix matériau</term>
<term>Transistor tunnel</term>
<term>Nanoélectronique</term>
<term>Effet tunnel</term>
<term>Courant fuite</term>
<term>Transistor effet champ</term>
<term>Courant continu</term>
<term>Masse effective</term>
<term>Bande conduction</term>
<term>Bande valence</term>
<term>Nanofil</term>
<term>Antimoniure d'indium</term>
<term>Phosphure d'indium</term>
<term>Composé binaire</term>
<term>Nitrure de gallium</term>
<term>Alliage Ge Si</term>
<term>Nanotube carbone</term>
<term>Germanium</term>
<term>8107V</term>
<term>8107D</term>
<term>InSb</term>
<term>InP</term>
<term>GaN</term>
</keywords>
</textClass>
</profileDesc>
</teiHeader>
<front>
<div type="abstract" xml:lang="en">When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field-effect transistors (FETs) and tunnel FETs. Therefore, a survey of materials in a nanowire geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge, and carbon nanotubes. The tunneling effective mass gives the best indication of the relative size of the tunnel currents when comparing two different materials of any type. The indirect-gap materials, Si and Ge, give the largest tunneling masses in the conduction band, and they give the smallest conduction band tunnel currents within the range of diameters considered. Si gives the lowest overall tunnel current for both the conduction and valence bands, and therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. A semianalytic approach to calculating tunnel current is demonstrated, which requires considerably less computation than a full-band numerical calculation.</div>
</front>
</TEI>
<inist>
<standard h6="B">
<pA>
<fA01 i1="01" i2="1">
<s0>0018-9383</s0>
</fA01>
<fA02 i1="01">
<s0>IETDAI</s0>
</fA02>
<fA03 i2="1">
<s0>IEEE trans. electron devices</s0>
</fA03>
<fA05>
<s2>59</s2>
</fA05>
<fA06>
<s2>8</s2>
</fA06>
<fA08 i1="01" i2="1" l="ENG">
<s1>Material Selection for Minimizing Direct Tunneling in Nanowire Transistors</s1>
</fA08>
<fA11 i1="01" i2="1">
<s1>SARWAT SYLVIA (Somaia)</s1>
</fA11>
<fA11 i1="02" i2="1">
<s1>PARK (Hong-Hyun)</s1>
</fA11>
<fA11 i1="03" i2="1">
<s1>ABUL KHAYER (M.)</s1>
</fA11>
<fA11 i1="04" i2="1">
<s1>ALAM (Khairul)</s1>
</fA11>
<fA11 i1="05" i2="1">
<s1>KLIMECK (Gerhard)</s1>
</fA11>
<fA11 i1="06" i2="1">
<s1>LAKE (Roger K.)</s1>
</fA11>
<fA14 i1="01">
<s1>Department of Electrical Engineering, University of California</s1>
<s2>Riverside, CA 92521-0204</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</fA14>
<fA14 i1="02">
<s1>Intel Corporation</s1>
<s2>Hillsboro, OR 97124-5961</s2>
<s3>USA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</fA14>
<fA14 i1="03">
<s1>Department of Electrical and Electronic Engineering, East West University</s1>
<s2>Dhaka 1212</s2>
<s3>BGD</s3>
<sZ>4 aut.</sZ>
</fA14>
<fA14 i1="04">
<s1>Network for Computational Nanotechnology, Purdue University</s1>
<s2>West Lafayette IN 47907</s2>
<s3>USA</s3>
<sZ>6 aut.</sZ>
</fA14>
<fA20>
<s1>2064-2069</s1>
</fA20>
<fA21>
<s1>2012</s1>
</fA21>
<fA23 i1="01">
<s0>ENG</s0>
</fA23>
<fA43 i1="01">
<s1>INIST</s1>
<s2>222F3</s2>
<s5>354000506691010100</s5>
</fA43>
<fA44>
<s0>0000</s0>
<s1>© 2012 INIST-CNRS. All rights reserved.</s1>
</fA44>
<fA45>
<s0>36 ref.</s0>
</fA45>
<fA47 i1="01" i2="1">
<s0>12-0318010</s0>
</fA47>
<fA60>
<s1>P</s1>
</fA60>
<fA61>
<s0>A</s0>
</fA61>
<fA64 i1="01" i2="1">
<s0>I.E.E.E. transactions on electron devices</s0>
</fA64>
<fA66 i1="01">
<s0>USA</s0>
</fA66>
<fC01 i1="01" l="ENG">
<s0>When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field-effect transistors (FETs) and tunnel FETs. Therefore, a survey of materials in a nanowire geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge, and carbon nanotubes. The tunneling effective mass gives the best indication of the relative size of the tunnel currents when comparing two different materials of any type. The indirect-gap materials, Si and Ge, give the largest tunneling masses in the conduction band, and they give the smallest conduction band tunnel currents within the range of diameters considered. Si gives the lowest overall tunnel current for both the conduction and valence bands, and therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. A semianalytic approach to calculating tunnel current is demonstrated, which requires considerably less computation than a full-band numerical calculation.</s0>
</fC01>
<fC02 i1="01" i2="X">
<s0>001D03C</s0>
</fC02>
<fC02 i1="02" i2="X">
<s0>001D03F04</s0>
</fC02>
<fC02 i1="03" i2="X">
<s0>001D03F18</s0>
</fC02>
<fC02 i1="04" i2="3">
<s0>001B80A07V</s0>
</fC02>
<fC03 i1="01" i2="X" l="FRE">
<s0>Choix matériau</s0>
<s5>01</s5>
</fC03>
<fC03 i1="01" i2="X" l="ENG">
<s0>Material selection</s0>
<s5>01</s5>
</fC03>
<fC03 i1="01" i2="X" l="SPA">
<s0>Selección material</s0>
<s5>01</s5>
</fC03>
<fC03 i1="02" i2="3" l="FRE">
<s0>Transistor tunnel</s0>
<s5>02</s5>
</fC03>
<fC03 i1="02" i2="3" l="ENG">
<s0>Tunnel transistors</s0>
<s5>02</s5>
</fC03>
<fC03 i1="03" i2="X" l="FRE">
<s0>Nanoélectronique</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="ENG">
<s0>Nanoelectronics</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="SPA">
<s0>Nanoelectrónica</s0>
<s5>03</s5>
</fC03>
<fC03 i1="04" i2="X" l="FRE">
<s0>Effet tunnel</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="ENG">
<s0>Tunnel effect</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="SPA">
<s0>Efecto túnel</s0>
<s5>04</s5>
</fC03>
<fC03 i1="05" i2="X" l="FRE">
<s0>Courant fuite</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="ENG">
<s0>Leakage current</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="SPA">
<s0>Corriente escape</s0>
<s5>05</s5>
</fC03>
<fC03 i1="06" i2="X" l="FRE">
<s0>Transistor effet champ</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="ENG">
<s0>Field effect transistor</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="SPA">
<s0>Transistor efecto campo</s0>
<s5>06</s5>
</fC03>
<fC03 i1="07" i2="X" l="FRE">
<s0>Courant continu</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="ENG">
<s0>Direct current</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="SPA">
<s0>Corriente contínua</s0>
<s5>07</s5>
</fC03>
<fC03 i1="08" i2="X" l="FRE">
<s0>Masse effective</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="ENG">
<s0>Effective mass</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="SPA">
<s0>Masa efectiva</s0>
<s5>08</s5>
</fC03>
<fC03 i1="09" i2="X" l="FRE">
<s0>Bande conduction</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="ENG">
<s0>Conduction band</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="SPA">
<s0>Banda conducción</s0>
<s5>09</s5>
</fC03>
<fC03 i1="10" i2="X" l="FRE">
<s0>Bande valence</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="ENG">
<s0>Valence band</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="SPA">
<s0>Banda valencia</s0>
<s5>10</s5>
</fC03>
<fC03 i1="11" i2="3" l="FRE">
<s0>Nanofil</s0>
<s5>22</s5>
</fC03>
<fC03 i1="11" i2="3" l="ENG">
<s0>Nanowires</s0>
<s5>22</s5>
</fC03>
<fC03 i1="12" i2="3" l="FRE">
<s0>Antimoniure d'indium</s0>
<s2>NK</s2>
<s5>23</s5>
</fC03>
<fC03 i1="12" i2="3" l="ENG">
<s0>Indium antimonides</s0>
<s2>NK</s2>
<s5>23</s5>
</fC03>
<fC03 i1="13" i2="X" l="FRE">
<s0>Phosphure d'indium</s0>
<s5>24</s5>
</fC03>
<fC03 i1="13" i2="X" l="ENG">
<s0>Indium phosphide</s0>
<s5>24</s5>
</fC03>
<fC03 i1="13" i2="X" l="SPA">
<s0>Indio fosfuro</s0>
<s5>24</s5>
</fC03>
<fC03 i1="14" i2="X" l="FRE">
<s0>Composé binaire</s0>
<s5>25</s5>
</fC03>
<fC03 i1="14" i2="X" l="ENG">
<s0>Binary compound</s0>
<s5>25</s5>
</fC03>
<fC03 i1="14" i2="X" l="SPA">
<s0>Compuesto binario</s0>
<s5>25</s5>
</fC03>
<fC03 i1="15" i2="X" l="FRE">
<s0>Nitrure de gallium</s0>
<s5>26</s5>
</fC03>
<fC03 i1="15" i2="X" l="ENG">
<s0>Gallium nitride</s0>
<s5>26</s5>
</fC03>
<fC03 i1="15" i2="X" l="SPA">
<s0>Galio nitruro</s0>
<s5>26</s5>
</fC03>
<fC03 i1="16" i2="3" l="FRE">
<s0>Alliage Ge Si</s0>
<s5>27</s5>
</fC03>
<fC03 i1="16" i2="3" l="ENG">
<s0>Ge-Si alloys</s0>
<s5>27</s5>
</fC03>
<fC03 i1="17" i2="3" l="FRE">
<s0>Nanotube carbone</s0>
<s5>28</s5>
</fC03>
<fC03 i1="17" i2="3" l="ENG">
<s0>Carbon nanotubes</s0>
<s5>28</s5>
</fC03>
<fC03 i1="18" i2="X" l="FRE">
<s0>Germanium</s0>
<s2>NC</s2>
<s5>29</s5>
</fC03>
<fC03 i1="18" i2="X" l="ENG">
<s0>Germanium</s0>
<s2>NC</s2>
<s5>29</s5>
</fC03>
<fC03 i1="18" i2="X" l="SPA">
<s0>Germanio</s0>
<s2>NC</s2>
<s5>29</s5>
</fC03>
<fC03 i1="19" i2="X" l="FRE">
<s0>8107V</s0>
<s4>INC</s4>
<s5>56</s5>
</fC03>
<fC03 i1="20" i2="X" l="FRE">
<s0>8107D</s0>
<s4>INC</s4>
<s5>57</s5>
</fC03>
<fC03 i1="21" i2="X" l="FRE">
<s0>InSb</s0>
<s4>INC</s4>
<s5>82</s5>
</fC03>
<fC03 i1="22" i2="X" l="FRE">
<s0>InP</s0>
<s4>INC</s4>
<s5>83</s5>
</fC03>
<fC03 i1="23" i2="X" l="FRE">
<s0>GaN</s0>
<s4>INC</s4>
<s5>84</s5>
</fC03>
<fC07 i1="01" i2="X" l="FRE">
<s0>Composé III-V</s0>
<s5>11</s5>
</fC07>
<fC07 i1="01" i2="X" l="ENG">
<s0>III-V compound</s0>
<s5>11</s5>
</fC07>
<fC07 i1="01" i2="X" l="SPA">
<s0>Compuesto III-V</s0>
<s5>11</s5>
</fC07>
<fC07 i1="02" i2="3" l="FRE">
<s0>Alliage semiconducteur</s0>
<s5>12</s5>
</fC07>
<fC07 i1="02" i2="3" l="ENG">
<s0>Semiconductor alloys</s0>
<s5>12</s5>
</fC07>
<fN21>
<s1>240</s1>
</fN21>
<fN44 i1="01">
<s1>OTO</s1>
</fN44>
<fN82>
<s1>OTO</s1>
</fN82>
</pA>
</standard>
</inist>
</record>

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